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ARM L2C-310 Model

Description

Level 2 Cache Controller


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SoC Designer PlusSwap 'N Play
L2C-310 Carbonized Model
Description The L2C-310 model is compiled directly from ARM's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Carbon’s SoC Designer Plus virtual prototype. This enables designers to perform accurate architectural analysis, performance optimization and pre-silicon firmware debug.
Performance Analysis Kits
Revisions r3p2, r3p1, r3p0, r2p0, r1p0
Access Process Pre Approval
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